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@@ -22,9 +22,9 @@ External (_SB_.PCI0.LPCB.EC0, DeviceObj) <- Rename this
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{
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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If (_OSI ("Darwin"))
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If (_OSI ("Darwin")) // Darwin = macOS
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{
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Return (0)
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Return (0) // Hides our real EC only when in macOS
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}
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Else
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{
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@@ -88,7 +88,7 @@ Scope (\_SB.PC00.LPC0) <- Rename this
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{
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If (_OSI ("Darwin"))
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{
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Return (0x0F)
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Return (0x0F) // Enable our Fake EC only when in macOS
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}
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Else
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{
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@@ -3,6 +3,10 @@
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So what this SSDT does is create a PNLF device for macOS to play with, specifically one with a hardware ID of `APP0002`. WhateverGreen will handle the rest of the work
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No configuration required for most, just drop the prebuilt file into your EFI: [SSDT-PNLF](https://github.com/khronokernel/Getting-Started-With-ACPI/blob/master/extra-files/SSDT-PNLF.aml)
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No configuration required for most, just drop the prebuilt file into your EFI:
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* [SSDT-PNLF](https://github.com/khronokernel/Getting-Started-With-ACPI/blob/master/extra-files/SSDT-PNLF.aml)
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* For most users
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* [SSDT-PNLF-CFL](https://i.applelife.ru/2019/12/463488_SSDT-PNLFCFL.aml.zip)
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* For Coffeelake users if the regular SSDT doesn't work, try SSDT-PNLF first and do not mix together
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Note: there are some rare cases where the iGPU is called `GPU0` or `VID`in the DSDT, you can double check by searching for `PCI0.GFX0`, `PCI0.VID` and `PCI0.GPU0`. Whichever shows up is your device
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@@ -1,6 +1,16 @@
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# Fixing System Clocks
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**For Intel 300 series chipsets only**
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**For Intel 300 series chipsets and newer**, this also includes X299 refreshes and Icelake laptops. Common machines:
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* X299X (10th Gen refresh)
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* B360
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* B365
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* H310
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* H370
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* Z370 (Gigabtye and AsRock boards with newer BIOS versions)
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* Z390
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* 400 series (Cometlake)
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* 495 series (Icelake)
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So on newer Intel 300 series motherboards, manufactueres started pushing for a new type of system clock: **AWAC**( **A** **W**eird **A**ss **C**lock). One small problem, macOS doesn't know what the hell an AWAC clock is instead only familiar with the legacy **RTC**(**R**eal **T**ime **C**lock). So we need to figure out how to bring back the old clock, thats where `SSDT-AWAC` and `SSDT-RTC0` come in:
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@@ -20,14 +30,14 @@ Note: AWAC actually stands for ACPI Wake Alarm Counter/Clock for those curious,
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To determine whether you need [SSDT-AWAC](https://github.com/acidanthera/OpenCorePkg/blob/master/Docs/AcpiSamples/SSDT-AWAC.dsl) or [SSDT-RTC0](https://github.com/acidanthera/OpenCorePkg/blob/master/Docs/AcpiSamples/SSDT-RTC0.dsl):
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* open your decompiled DSDT and search for `Device (AWAC)`
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* If nothing shows then no need to continue and no need for this SSDT as you have no AWAC. Otherwise, continue on!
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* If you get a result then you have an `AWAC` system clock present, then continue with the next search for `STAS ==`:
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* If **nothing shows up** then no need to continue and **no need for this SSDT** as you have no AWAC. **Otherwise, continue on!**
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* If you get a result then you have an `AWAC` system clock present, then continue with the **next search for `STAS ==`**:
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As you can see we found the `STAS ==` in our DSDT, this means we're able to force enable our Legacy RTC. In this case, [SSDT-AWAC](https://github.com/acidanthera/OpenCorePkg/blob/master/Docs/AcpiSamples/SSDT-AWAC.dsl) will be used As-Is with no modifications required. Just need to compile. Note that `STAS` may be found in AWAC first instead of RTC like in our example, this is normal.
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For systems where no `STAS` shows up **but** you do have `AWAC`, you can use [SSDT-RTC0](https://github.com/acidanthera/OpenCorePkg/blob/master/Docs/AcpiSamples/SSDT-RTC0.dsl) though you will need to check the naming of LPC in your DSDT
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For systems where **no `STAS`** shows up **but** you do have `AWAC`, you can use [SSDT-RTC0](https://github.com/acidanthera/OpenCorePkg/blob/master/Docs/AcpiSamples/SSDT-RTC0.dsl) though you will need to check the naming of LPC in your DSDT
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By default the SSDT uses `LPCB`, you can check what your system uses by just searching for `Name (_ADR, 0x001F0000)`. This address is used for Low Pin Count devices(LPC) but the device name can vary between `LPCB`, `LBC` or `LBC0`:
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@@ -1,6 +1,14 @@
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# Fixing NVRAM
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This SSDT is required for all B360, B365, H310, H370, Z390 motherboards, it specifically brings back NVRAM support and requires very little configuration for the end user.
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This SSDT is required for all "true" 300 series motherboards and newer(Z370 is excluded), it specifically brings back NVRAM support and requires very little configuration for the end user.
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* B360
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* B365
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* H310
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* H370
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* Z390
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* 400 series (Cometlake)
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* 495 series (Icelake)
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By default it uses `PCI0.LPCB` for the PCI and LowPinCount path. The device names can vary between `PC00` and `PCI0` for PCI path and `LPCB`, `LBC` and `LBC0` for LowPinCount path. To see what you have:
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